The present invention relates to an amplitude detecting circuit for detecting an amplitude of an output signal of a digital filter, for example, used in a system such as the radio communications, cable communications, signal processing or control.
Previously, in a system using a digital filter, for example, in order to perform the automatic gain control or the peak suppression control, it is necessary to detect the amplitude of an output signal of the above-described digital filter.
FIG. 9 is a block diagram showing one example of a conventional automatic gain control circuit. In FIG. 9, an input signal X(k) is amplified by an amplifier circuit 171, and converted into a digital signal by an A/D converter circuit 172, and after that, it is supplied to a digital filter 175. In the digital filter 175, a given filter processing is applied to the supplied digital signal, and after that, it is output as an output signal Y(k). Furthermore, the digital signal from the A/D converter circuit 172 is also supplied to an amplitude detecting circuit 174, and an amplitude of the output signal Y(k) from the digital filter 175 is detected. This amplitude information is supplied to a gain control circuit 173, and a gain control signal corresponding to the above-described amplitude information is created. Then, this gain control signal is supplied to the amplifier circuit 171. That is, the gain control signal created on the basis of the amplitude information of the detected output signal Y(k) is fed back to the amplifier circuit 171, so that the gain control may automatically be performed.
Here, concretely, the digital filter 175 has such a structure as shown in FIG. 10. That is, the digital filter 175 is a non-recursive digital filter with sixteen taps, and it comprises sixteen delay units 191, sixteen multipliers 192 respectively connected to the above-described delay units 191 and having coefficients h0 to h15 set, and one adder 193 respectively connected to the above-described multipliers 192.
Furthermore, the digital filter 175 has such an impulse response characteristic as shown in FIG. 11, and a non-recursive digital filter (transfer function H(z)) having a structure corresponding to the total of this impulse response (hereafter, referred to as xe2x80x9cfull impulse responsexe2x80x9d) is used as the amplitude detecting circuit 174. That is, as shown in FIG. 10, the amplitude detecting circuit 174 comprises sixteen delay units 194, sixteen multipliers 195 respectively connected to the above-described delay units 194 and having coefficients h0 to h15 set, and one adder 196 respectively connected to the above-described multipliers 195. Thus, in a conventional automatic gain control circuit, the amplitude of an output signal Y(k) has been detected by using a digital filter having the same structure as the digital filter 175, as the amplitude detecting circuit 174.
On the other hand, FIG. 12 is a block diagram showing one example of a conventional peak suppression circuit. In FIG. 12, an input signal X(k) is delayed by a given time in a delay circuit 183, and supplied to a digital filter 184. In the digital filter 184, a given filter processing is applied to the supplied delayed input signal, and after that, it is output to as an output signal Y(k). Furthermore, the input signal X(k) is also supplied to an amplitude detecting circuit 181, and the amplitude of an output signal Y(k) from the digital filter 184 is detected. This amplitude information is supplied to a peak suppression control circuit 182, and a peak suppression control signal corresponding to the above-described amplitude information is created. Then, this peak suppression control signal is supplied to the digital filter 184. That is, the peak suppression control signal created on the basis of the amplitude information of the detected output signal Y(k) is fed forward to the digital filter 184, so that the control of the peak suppression may automatically be performed.
Here, the digital filter 184 has such a structure as shown in FIG. 10, similarly to the above-described digital filter 175. Furthermore, the amplitude detecting circuit 181 also has such a structure as shown in FIG. 10, similarly to the above-described amplitude detecting circuit 174. That is, in the conventional peak suppression circuit, the amplitude of an output signal Y(k) has been also detected by using a digital filter having the same structure as the digital filter 184, as the amplitude detecting circuit 181.
However, in the case of performing such a feed back control where the input level to the digital filter 175 is controlled on the basis of the detection results of the amplitude of an output signal from the digital filter 175 like the conventional automatic gain control circuit, the detection of the amplitude is performed by using the amplitude detecting circuit 174 that is a digital filter having the same structure as the digital filter 175, and therefore, the processing delay according to the amplitude detection is large, and accordingly, the time constant of the feed back becomes large, and such a problem that the high speed tracking is impossible has been created. Furthermore, another digital filter having the same structure becomes necessary besides the digital filter 175 used for the actual signal processing, and the increase of the circuit size has been caused.
Furthermore, in the case where the feed forward control to the digital filter 184 is performed on the basis of the detection results of the amplitude of an output signal of the digital filter 184 like the conventional peak suppression circuit, it is necessary to determine the control information (peak suppression control signal) before performing the signal processing by the digital filter 184, and therefore, it has been necessary to delay the supply of an input signal into the digital filter 184 by the delay circuit 183, expecting the processing delay time according to the amplitude detection in the amplitude detecting circuit 181. In the case of a conventional peak suppression circuit, the amplitude of an output signal is detected by the amplitude detecting circuit 181 that is a digital filter having the same structure as the signal processing digital filter 184, and therefore, the processing delay for the amplitude detection is large, and as a result, the processing delay for the signal processing has also become large. Furthermore, in this conventional peak suppression circuit, another digital filter having the same structure is also necessary besides the digital filter 184 used for the actual signal processing, and the increase of the circuit scale has been caused.
The present invention has been made due to such conventional problems, and it is an object to provide an amplitude detecting circuit in which the processing delay according to the amplitude detection of an output signal of the signal processing digital filter is small, and the circuit scale can be decreased.
In order to attain the above-described object, the amplitude detecting circuit according to a first aspect of the present invention comprises a simple digital filter having a plurality of taps corresponding to the part where the energy is concentrated in the full impulse response of a non-recursive signal processing digital filter, and it is characterized in that it supplies the same signal as a signal supplied to the above-described signal processing digital filter, to the above-described simple digital filter, and that it approximately detects an output amplitude of the above-described signal processing digital filter as an output of the above-described simple digital filter.
According to a second aspect of the present invention, when a signal making the output amplitude maximum is supplied to the above-described signal processing digital filter, the plurality of taps of the above described simple digital filter are selected from the taps of the above described signal processing digital filter located around the tap with a coefficient of the maximum absolute value among all taps of the signal processing digital filter, and that the taps are selected so that the ratio of the sum total of absolute values of coefficients of selected taps to the sum total of absolute values of coefficients of all taps is greater than or equal to some fixed value.
According to a third aspect of the present invention, the above-described fixed value is set according to the required detection accuracy of the output amplitude.
According to a fourth aspect of the present invention, the above-described simple digital filter comprises an amplitude storing part for storing the information of an output amplitude corresponding to a pattern of a supplied signal, and that the information of the output amplitude read out of the above-described amplitude storing part is made an output of the above-described simple digital filter.
According to a fifth aspect of the present invention, the above-described simple digital filter comprises a peak generating pattern storing part for storing a peak generating pattern that is a pattern of a signal generating an output amplitude of a given value or more, and that a peak detection signal is output from the above-described peak generating pattern storing part, when a pattern of the supplied signal agrees with the above-described peak generating pattern.